ResearchSpace

Leakage current minimisation and power reduction techniques using sub-threshold design

Show simple item record

dc.contributor.author Tsague, HD
dc.contributor.author Twala, B
dc.date.accessioned 2016-04-22T07:29:51Z
dc.date.available 2016-04-22T07:29:51Z
dc.date.issued 2015-11
dc.identifier.citation Tsague, H.D and Twala, B. 2015. Leakage current minimisation and power reduction techniques using sub-threshold design. The International Conference on Information Society (i-Society), 9-11 November 2015, London, United Kingdom en_US
dc.identifier.uri http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7366877
dc.identifier.uri http://hdl.handle.net/10204/8517
dc.description The International Conference on Information Society (i-Society), 9-11 November 2015, London, United Kingdom. Due to copyright restrictions, the attached PDF file only contains the abstract of the full text item. For access to the full text item, please consult the publisher's website en_US
dc.description.abstract Low power IC solutions are in great demand with the rapid advancement of handheld devices, wearables, smart cards and radio frequency identification bringing a massive amount of new products to market that all have the same primary need: Powering the device as long as possible between the need to recharge the batteries while at the same time dramatically decreasing the device leakage currents. The use of sub-threshold techniques can be a powerful way to create circuits that consume dramatically less energy than those built using standard design practices. In this research, a SOI device was built to compare their electrical characteristics using Silvaco software. The comparisons were focused on three main electrical characteristics that are threshold voltage, sub-threshold voltage and leakage current. It was found that SOI devices are ideal candidates for low power operation. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.relation.ispartofseries Workflow;16374
dc.subject Power dissipation en_US
dc.subject Weak inversion en_US
dc.subject Ultra-low-power en_US
dc.subject Leakage currents en_US
dc.subject Power analysis en_US
dc.title Leakage current minimisation and power reduction techniques using sub-threshold design en_US
dc.type Conference Presentation en_US
dc.identifier.apacitation Tsague, H., & Twala, B. (2015). Leakage current minimisation and power reduction techniques using sub-threshold design. IEEE. http://hdl.handle.net/10204/8517 en_ZA
dc.identifier.chicagocitation Tsague, HD, and B Twala. "Leakage current minimisation and power reduction techniques using sub-threshold design." (2015): http://hdl.handle.net/10204/8517 en_ZA
dc.identifier.vancouvercitation Tsague H, Twala B, Leakage current minimisation and power reduction techniques using sub-threshold design; IEEE; 2015. http://hdl.handle.net/10204/8517 . en_ZA
dc.identifier.ris TY - Conference Presentation AU - Tsague, HD AU - Twala, B AB - Low power IC solutions are in great demand with the rapid advancement of handheld devices, wearables, smart cards and radio frequency identification bringing a massive amount of new products to market that all have the same primary need: Powering the device as long as possible between the need to recharge the batteries while at the same time dramatically decreasing the device leakage currents. The use of sub-threshold techniques can be a powerful way to create circuits that consume dramatically less energy than those built using standard design practices. In this research, a SOI device was built to compare their electrical characteristics using Silvaco software. The comparisons were focused on three main electrical characteristics that are threshold voltage, sub-threshold voltage and leakage current. It was found that SOI devices are ideal candidates for low power operation. DA - 2015-11 DB - ResearchSpace DP - CSIR KW - Power dissipation KW - Weak inversion KW - Ultra-low-power KW - Leakage currents KW - Power analysis LK - https://researchspace.csir.co.za PY - 2015 T1 - Leakage current minimisation and power reduction techniques using sub-threshold design TI - Leakage current minimisation and power reduction techniques using sub-threshold design UR - http://hdl.handle.net/10204/8517 ER - en_ZA


Files in this item

This item appears in the following Collection(s)

Show simple item record